Project Description

This project contains a pipelined and non-pipelined version of a 5-stages MIPS-compatible CPU. The CPU is programmed using Verilog. Moreover, a testbench with a reference CPU coded using C++ is included. The testbench consists of automatically generated testcases for each required instruciton and several general testcases containing a mixture of different instructions.

This project is a part of the Instruction Architecture and Compiler course in 2nd Year Imperial College London EIE department. The CPU (non-pipelined version) passed 98% of the testcases.